In a switching circuit, for example, using MOS transistors, when each transistor is switched from ON state to OFF state, electric charge stored in a channel region of the transistor moves into a source region or a drain region due to a phenomenon known as clock leakage. Herein, “clock leakage” is assumed to include charge injection and clock feedthrough.
The clock leakage occurring when the MOS transistor varies from ON state to OFF state causes variations in the potential at a high-impedance node, for example, in a sample-and-hold circuit or a comparator circuit.
Charge injection is a phenomenon in which electric charge (electrons or holes) forming a channel when a transistor acting as a switching device is ON is moved into the source or drain of the transistor when the transistor is turned off. Clock feedthrough is a phenomenon in which, as the gate potential varies from a high level (H) to a low level (L), the potential is affected by an electrostatic effect arising from the parasitic capacitance between the gate and drain or between the gate and source when the transistor is an nMOS transistor, for example.
A semiconductor device is known which consists of a switching circuit having MOS transistors. The switching circuit has a main switching transistor and a canceling transistor having a channel width that is equal to half of the channel width of the main switching transistor.
In this semiconductor device, when the main switching transistor is turned from on to off, the effect of clock leakage is undone by performing an operation for switching the canceling transistor from off to on, i.e., the transistor is operated in a reverse-phase with respect to the switching operation of the main switching transistor.
FIGS. 1A and 1B are diagrams illustrating charge injection and a countermeasure against it. FIG. 1A illustrates the manner in which a main switching transistor 1 is varied from on to off. FIG. 1B illustrates the operation of a canceling transistor 2 when the main switching transistor 1 is varied from on to off. In FIGS. 1A and 1B, the main switching transistor 1 and canceling transistor 2 are nMOS transistors.
As illustrated in the left portion of FIG. 1A, the main switching transistor 1 has a gate G1. A high level signal H is applied to the gate G1, and the transistor conducts (ON). At this time, a channel CH1 is formed by electrons between source S1 and drain D1 opposite to the gate G1 within the substrate.
As illustrated in the right portion of FIG. 1A, when the high level signal H applied to the gate G1 goes low (L), the main switching transistor 1 varies from on to off. As a result, the channel CH1 disappears. Then, electric charge Qd forming the channel CH1 moves into the source 51 and drain D1 of the switching transistor 1. Electric charge Qd/2 flows into both the source and drain.
As illustrated in the left portion of FIG. 1B, when the main switching transistor 1 is ON, a low level signal L is applied to the gate G2 of the canceling transistor 2, turning the transistor off.
As illustrated in the right portion of FIG. 1B, when the main switching transistor 1 varies from on to off, the signal applied to the gate G2 of the canceling transistor 2 is switched from low level signal L to high level signal H. Consequently, a channel CH2 is formed between the source S2 and drain D2 opposite to the gate G2 of the canceling transistor 2 within the substrate, turning on the canceling transistor 2.
The canceling transistor 2 is half in size to the main switching transistor 1. The electric charge in the channel CH2 when the canceling transistor 2 is ON is half of the electric charge Qd in the channel CH1 when the main switching transistor 1 is ON.
The electrodes of the canceling transistor 2 are coupled with the source S1 or drain D1 of the main switching transistor 1. For example, the source S2 and drain D2 are shorted and coupled.
The electric charge (Qd/2) in the channel CH1 disappearing when the main switching transistor 1 varies from on to off is absorbed by the channel CH2 formed when the canceling transistor 2 varies from off to on. Thus, the effect of release of electric charge is canceled.
In FIGS. 1A and 1B, the main switching transistor 1 and canceling transistor 2 are nMOS transistors. They may also be pMOS transistors.
FIGS. 2A-2C illustrate a countermeasure against clock feedthrough. FIG. 2A illustrates the manner in which the main switching transistor 1 and the canceling transistor 2 are coupled.
FIG. 2B illustrates the statuses of the main switching transistor 1 and the canceling transistor 2 when the high level signal H is applied to the gate 1G and the main switching transistor 1 is ON.
FIG. 2C illustrates the statuses of the main switching transistor 1 and the canceling transistor 2 when the signal applied to the gate G1 is switched from high level H to low level L, turning off the main switching transistor 1.
Also, in FIGS. 2A to 2C, an nMOS transistor is illustrated as an example of each of the main switching transistor 1 and canceling transistor 2. The present invention is not limited to this configuration.
As illustrated in FIG. 2A, the source S2 and drain D2 of the canceling transistor 2 are shorted and coupled with the drain D1 of the main switching transistor 1.
The canceling transistor 2 is substantially half in gate width of the main switching transistor 1. A buffer amplifier that reshapes and outputs the waveform of the signal at the drain D1 of the main switching transistor 1 is indicated by reference numeral 3.
In the main switching transistor 1, the gate G1 and drain D1 are electrostatically coupled through the gate capacitance. Similarly, in the canceling transistor 2, the gate G2, source S2, and drain D2 are capacitively coupled through the gate capacitance. The drain D1 of the main switching transistor 1 is coupled with the source S2 and drain D2 of the canceling transistor 2.
When the main switching transistor 1 varies from ON state as illustrated in FIG. 2B to OFF state as illustrated in FIG. 2C, the canceling transistor 2 varies from off to on.
That is, the signal applied to the gate G2 of the canceling transistor 2 is switched from low level L to high level H, and variations in the potential due to electrostatic coupling of the main switching transistor 1 are absorbed by the electrostatic coupling of the canceling transistor 2.
There has been proposed a sample-and-hold circuit as a sampling switch, the circuit having at least two transistors. The opposite ends of the switch are coupled in parallel between a terminal to which an analog input voltage is applied and one end of a holding capacitor (Japanese Laid-open Patent Publication No. 11-224496).
In this sample-and-hold circuit, when the analog input voltage is sampled, one transistor of the at least two transistors is turned off and then the other transistor is turned off with a delay. Consequently, the sampling speed is increased. Also, the sampling accuracy is enhanced.
A circuit for adjusting the offset of an operational amplifier is also proposed, the circuit having a pair of MOS transistors for differential operation. The MOS transistors together form a differential amplifier. A voltage for setting an offset is applied to the substrate of the MOS transistors to calibrate the offset (Japanese Laid-open Patent Publication No. 11-068476).
The calibration of the offset is performed by applying the same voltage to the gates of the MOS transistors of a pair for differential operation and applying a voltage corresponding to the number of closed switches mounted in the MOS transistors to the substrate.
An analog signal processor used in an ADC realizing higher speeds and higher accuracy is also proposed (Japanese Laid-open Patent Publication No. 2002-033663).
The analog signal processor has a voltage selection portion for selecting a given reference voltage for comparison from a plurality of reference voltages for comparison and an arithmetic portion for arithmetically processing an analog input signal and the given reference voltage for comparison. Furthermore, the number of decision points is at least one more than the number of comparison reference voltages in the processor. In addition, the processor has a comparison portion to which the output from the arithmetic portion is applied and a coupling portion for controlling the coupling between the arithmetic portion and the comparison portion.
The arithmetic portions have correctable first signal processing portions. The number of the arithmetic portions is greater than the number necessary for the comparison reference voltages by at least M (where M is a natural number). The coupling portion couples the arithmetic portions having the first signal processing portions not engaged in corrective operation with the comparison portion when N (where N is a natural number; N≦M) of the first signal processing portions are engaged in corrective operation.
This analog signal processor suppresses the number of devices by the use of interpolation and may correct an error produced in background by the interpolation. Furthermore, the processor may eliminate the effects of variations among the devices by a correction.